The present invention relates to integrated circuits and, more particularly, to static random access memory (SRAM) cell design. A major objective of the present invention is to provide for denser SRAM memory circuits.
Much of modern progress is associated with the increasing miniaturization of integrated circuits made possible by advances in semiconductor processing technology.. This miniaturization has provided integrated circuits of greater functionality, due in part to the greater number of circuits per integrated circuit, and greater speed, due in part to shorter distances between circuit elements.
The transistor is the most pervasive circuit element in integrated circuits, serving as switches, amplifiers and detectors. Both MOSFET and bipolar technologies can be used to fabricate transistors. Of the two, MOSFET technology is more prevalent because of its lower power requirements. Lower power means less problem with heat dissipation, which looms as a major concern as circuits become increasingly dense. In addition, lower power provides for longer battery lifetimes in portable devices.
A MOSFET includes a source, a drain, a channel, a gate, and an insulator electrically isolating the gate and the channel. Typically, the source and drain are commonly doped semiconductor regions separated by the channel. The voltage at the gate controls the conductivity of the channel, and thus the flow of current between the source and the drain.
"MOSFET" stands for "metal-oxide-silicon field-effect transistor". The "field effect" is the effect of the field induced by the gate voltage on the channel conductivity. "Metal-oxide-silicon" describes the gate structure for transistors in which metal is used for the conductive gate. Since doped polysilicon is the prevalent gate material today, "MOS" can be considered a well-established misnomer.
The earliest MOS transistors were PMOS transistors, which have positively-doped (p-type) sources and drains. Subsequently, NMOS transistors, which have negatively-doped (n-type) sources and drains have become more prevalent. CMOS technology utilizes both NMOS and PMOS transistors to provide circuits with exceptionally low power requirements. Most recently, BiCMOS technology combines bipolar, NMOS and PMOS transistors on a single integrated circuit to make the most of the advantages of each transistor type.
While modern CMOS circuits no longer use metal gates, metal is still the prevalent interconnect material between transistors. Layers of interconnect metal, such as aluminum, are used to define the functional connections among transistors. At least two levels of metal are usually required to provide cross-overs. Depending on the routing complexity, additional metal layers can be required. Insulating layers, for example of silicon dioxide, electrically isolate the metal layers from each other and from underlying local interconnects and transistor source/drain regions. Metal vias are formed through the insulating layers to provide for electrical connections among the metal and local interconnects and source/drain regions.
While not as conductive as metal, doped silicon and polysilicon can be used for local electrical connections to reduce the number and the complexity of the metal layers and to reduce the number of vias required. The resistivity of these interconnects can be reduced by forming silicide on the doped silicon and polysilicon interconnects. For example, titanium can be deposited over the conductor. The titanium can then be heated, causing the titanium to react with the silicon to form a silicide.
Since the silicide only forms on silicon and not on silicon dioxide, the silicide is self-aligning. Self-aligned features are distinguished from features that rely on the proper registration of successive photolithography masks for alignment. Silicide contacts are not subject to mask misregistration, and thus provide for more precise feature location and increased circuit density.
The silicide is typically formed in a nitrogen ambient to prevent unwanted oxidation. Titanium not in contact with silicon is converted to titanium nitride. This titanium nitride is typically etched away during silicide processing.
However, since titanium nitride is conductive, it can be patterned to provide local interconnections as disclosed in "VLSI Local Interconnect Level Using Titanium Nitride" by Thomas Tang, Che-Chia Wei, Roger Haken, Thomas Holloway, Chang-Feng Wan, and Monte Douglas, IEDM, 1985, pp. 590-593. Tang et al. discloses novel layouts for an inverter and a six-transistor CMOS SRAM cell. The inverter uses titanium-nitride to connect a polysilicon local interconnect to the respective drains of a PMOS transistor and an NMOS transistor. The memory cell also uses titanium nitride interconnects to connect gate polysilicon to source/drain regions. The resulting memory cell, illustrated in FIG. 7b of Tang et al., consumes about 20% less area than the comparable conventional memory cell, illustrated in FIG. 7a.
The disclosed six-transistor cell employs five titanium nitride local interconnects, each electrically connecting a transistor gate to an active region (source or drain) of another transistor. Accordingly, there are a total of 10 silicide contacts. In addition, substrate diffusion and polysilicon local interconnects are employed.
While the silicide contacts are self-aligning, the titanium nitride is subject to mask misregistration. To minimize misalignment, titanium nitride interconnects can be made larger. In this event, however, the titanium-nitride interconnects themselves impose a limit on further improvements in circuit density. In addition, silicide contacts can fail. Having a large number of silicide contacts per cell can reduce manufacturing yields, and thus increase the costs of the integrated circuits.
Since many integrated circuits include very large numbers of SRAM cells, any reduction of cell dimensions can yield large benefits in terms of overall circuit density. What is needed is a memory cell design that can provide for greater circuit densities. In addition, improved circuit reliability and lower circuit costs are desired.